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How much power will I save?

Power savings can exceed 30% of total chip power, depending on extent of deployment. Typical power savings for multi-GHz designs are around 15% of total chip power.

What is the area penalty?

2% to 5% when using top-level metal layer for the inductors.

What is the performance penalty?

Absolutely none.

Does Cyclos Resonant Clock Mesh technology require any
special libraries or process steps?


Is Cyclos RCM technology compatible with standard EDA tool flows?

Yes, one can use any existing tools along with the Cyclos RCM Compiler to integrate the Cyclos power-saving technology into high-performance semiconductors

Does Cyclos RCM technology support dynamic frequency scaling?

Yes, either incremental or deep scaling will work.

Can I use voltage islands and voltage scaling?

Yes, both are supported.

Does my testing process change?

No, same wafer and package testing as before.

How can I join the Cyclos team?

We are always looking for hardware and software engineers with exceptional talent and a passion to innovate. Please submit your career inquiry here.