Berkeley, CA – February 20, 2012 – Cyclos Semiconductor, the inventor and only supplier of resonant clock mesh technology for commercial IC designs, today announced at the International Solid State Circuits Conference (ISSCC) in San Francisco, CA that AMD has successfully implemented Cyclos’ low-power semiconductor intellectual property (IP) in the AMD x86 core destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP to reduce power consumption demonstrates the commitment AMD has made to provide its customers with not only class-leading APU performance but also with the lowest possible power consumption.
New Resonant Clock Platform offers IP cell libraries for low-power resonant-clock chips
Berkeley, CA – June 9, 2008 – Cyclos Semiconductor, Inc., a privately-held start-up company and pioneer of resonant-clock design technologies for ultra-low-power devices, today announced the availability of the Resonant Clock (RCL) Platform for low-power ASIC design. Targeting applications in the embedded, mobile, medical, and compute server space with extreme low-power and low-electromagnetic-interference requirements, RCL is the industry’s first platform IP for standard-cell-based design and seamless interfacing of resonant-clocked chips. Currently, RCL has been silicon-verified in conjunction with the Cyclify standard-cell design flow on the standard-threshold UMC 130nm bulk silicon process.
Cadence Encounter Platform is selected for industry’s first high-performance power efficient resonant clocking design methodology
San Jose, CA, and Berkeley, CA – June 9, 2008 –Cyclos Semiconductor, Inc., a privately-help start-up company and pioneer of resonant-clock design technologies for ultra-low-power devices, today announced the Cyclify back-end design flow for resonant-clock ASIC design. The breakthrough Cyclify flow uses the Cadence Low Power Solution to enable design of low-power applications in the embedded, mobile, medical, and compute server space with extreme low-power and low-electromagneticinterference requirements. Used in conjunction with the Cyclos Resonant-Clock (RCL) Platform, Cyclify is the industry’s first back-end design flow for seamlessly integrating resonant-clocking into ASIC designs, addressing the needs of designers for fast turnaround times, robust design, and high-performance low-power implementations.
New implementation methodology for ARM processors offers new levels of power efficiency and performance
Berkeley, CA – June 9, 2008 – Cyclos Semiconductor, Inc., a privately-held startup and the pioneering provider of resonant-clock design technologies for ultra-lowpower devices, today announced the industry’s first proof of concept processor implementation using the Cyclos™ Resonant-Clock (RCL) Platform™ and Cyclify™ standard-cell design flow. The project, code-named ELIZABETH, is a resonantclocked implementation of the ARM926EJ-S™ processor, providing silicon validation of the benefits resulting from the deployment of the RCL Platform in a commercial standard-cell processor design, and demonstrating the Cyclify flow on industry standard soft IP.