Technology
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Resonant-clock
4+GHz
Piledriver core
(ISSCC 2012) PDF

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Resonant-clock
ARM926EJ-S core
(ESSCIRC 2009) PDF

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It's time to change
the clocks
(white paper)PDF

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At the heart of all Cyclos technologies is the principle that electrical energy can be reclaimed and recycled in digital semiconductors, in much the same way that kinetic energy is reclaimed and recycled in hybrid automobiles. Just as hybrid cars use less gasoline to transport you the same distance, semiconductors that incorporate Cyclos technologies use less power to perform the same computations as their conventional counterparts.

RMC Schematic

Designers of high-performance semiconductors can reduce the power consumption of their designs by 10%, 20%, or even 30% with the use of the Cyclos Resonant Clock Mesh technology. The Cyclos RCM technology introduces inductive-capacitive oscillators in mesh-based high-performance clock distribution networks to provide frequency-locked, high-performance, high-precision timing while dissipating almost no power. In addition to ultra-low power, the Cyclos technology yields clock networks with increased robustness to process and environmental variations in current and upcoming nanometer technologies.

The potential of a technology to reduce power consumption is meaningless if the technology requires changes in the specification/design/verification flow that have negative impact on productivity or time-to-market. Fortunately, the Cyclos RCM technology can be deployed by adding Cyclos drop-in IP and the Cyclos RCM Compiler to any standard synthesis-APR flow, resulting in high-performance semiconductors with dramatically reduced power consumption.

Chip The real-world benefits of Cyclos RCM Platform were initially demonstrated by the Cyclos Elizabeth test-chip. With two ARM926EJ-S microcontrollers integrated onto a single die, Elizabeth yields running-silicon comparison of the power and performance of a conventionally-clocked ARM926EJ-S with an otherwise identical one realized with the RCM Platform. The results? Over 25% lower power dissipation, without reductions in any other aspect of chip performance.

Chip AMD’s 4+ GHz x86-64 core code-named “Piledriver” is the first high-volume processor core to deploy the Cyclos RCM technology to reduce clock power while maintaining an ultra-low clock-skew target. The Cyclos resonant clock mesh relies on fully-integrated inductors to reduce average power consumption by 5% to 10% and improve peak-power-constrained performance with minimal area impact.